Processing systems, including pipelined systems, generally utilize an arbiter to arbitrate among the devices requesting access to a shared resource over a system bus. When a requesting device desires access to the shared resource, the requesting device generally generates a request and waits for a grant. One problem with this approach is the latency involved with such requests. This is especially a problem for memory devices, such as memory controllers, because latency and bus-bandwidth limitations may result in delays that impact system-level operations.
Thus there are general needs for systems and methods that help reduce the effects of latency and increase bus-usage efficiency.